The present invention relates to semiconductor integrated circuit devices and methods for fabricating the same. More particularly, the present invention relates to measurements for improving alignment accuracy in processing fuses that are used for circuits such as circuits for redundancy replacement or circuits for function adjustment.
Recently, with progress in microfabrication technology of semiconductor processing, system-on-a-chips including semiconductor memory devices (hereinafter, referred to as “memory circuits”) such as large-capacity dynamic random access memories (hereinafter, referred to as “DRAMs”) or large-capacity static random access memories (hereinafter, referred to as “SRAMs”) have been developed as semiconductor integrated circuit devices. To achieve further integration in the semiconductor integrated circuit devices, multilevel interconnection technology has been adopted into interconnection that connects circuit elements.
On the other hand, as the memory circuit increases in capacity due to the progress in the microfabrication technology, a larger number of defective bits causing malfunction of the memory circuit are created by, for example, fine dusts produced during a fabrication process. The presence of the defective bits makes the overall semiconductor integrated circuit device inoperable, thus decreasing the production yield.
One solution for eliminating the decrease in production yield caused by the defective bits is a technique of redundancy replacement. In this technique of redundancy replacement, the memory circuit and a spare memory bit are previously formed within a chip at the same time. Then, when a defective memory bit occurs, the defective memory bit is replaced with the spare memory bit so that all the bits corresponding to the memory capacity required for the memory circuit are constituted by conforming bits. That is to say, the technique of redundancy replacement is a technique for repairing defective bits. In this case, connections of an access signal between the defective memory bit and the spare memory bit are switched using a laser machining technique, i.e., irradiating a fuse portion of the circuit for redundancy replacement on the chip with a laser beam so that the fuse portion is burnt out and blown.
Conventionally, in a semiconductor integrated circuit device with a multilevel interconnection structure, a bit line, made of a polycide film as a stack of polysilicon and tungsten silicide, and a fuse wire are formed at the same time. If the multilevel interconnection has three or more levels, an aluminum alloy interconnect made of an AlCu film (i.e., an aluminum and copper alloy film) containing aluminum as a main component is used, so that the fuse wire is subjected to laser machining concurrently with an aluminum alloy interconnect formed in the uppermost layer.
On the other hand, as the interconnection has been downsized, a copper film, which can be downsized and has a low resistivity, has been used as an interconnect material, instead of the aluminum alloy film, for the purposes of suppressing the delay in circuit operation due to the rise in interconnect resistance and suppressing increase in heat generated by current. However, if a pad that is connected to a lead of a package via a metal fine wire is made of the copper film, the surface of the copper film is likely to be oxidized during assembly of a product. Accordingly, for ordinary wire bonding, it is impossible to connect the copper film to the metal fine wire because an oxide film has been formed on the surface of the copper. Thus, an aluminum alloy pad electrode used as an external-component-connecting pad electrode is formed only on a lead electrode part of the copper interconnect.
In the semiconductor integrated circuit device including the aluminum alloy pad electrode formed on the lead electrode of the copper interconnect, an alignment mark that is used during a probe test process for evaluating electric properties or an assembly process such as chip dicing or wire bonding is made of an aluminum alloy film forming the aluminum alloy pad electrode, as in a known semiconductor integrated circuit device with a multilevel interconnection structure including an aluminum alloy interconnect. Thus, the alignment mark and the aluminum alloy pad electrode are formed at the same time.
Hereinafter, alignment marks for use in a known semiconductor integrated circuit device including a copper interconnect and an aluminum alloy pad electrode will be described.
FIG. 8 is a cross-sectional view showing a structure of an interconnect layer in a known system-on-a-chip including a memory such as a DRAM or SRAM (a semiconductor integrated circuit device) with a function of redundancy replacement.
As shown in FIG. 8, the known semiconductor integrated circuit device includes: Si substrate 101; multilevel interconnect layer 102 formed on the Si substrate 101 by a process such as a dual or single damascene process; and dielectric film (an uppermost interlevel dielectric film) 103 formed on the multilevel interconnect layer 102. The uppermost metal layer 102a of the multilevel interconnect layer 102 includes: external-component-connecting wire 111; ordinary wire 112; fuse wire 113; and stepper alignment mark 114. The dielectric film 103 has an opening over the external-component-connecting wire 111. An external-component-connecting pad electrode 121 is formed on part of the dielectric film 103 to extend over the external-component-connecting wire 111 via the side face of the opening. An inorganic passivation film 104 made of, for example, a silicon nitride film and an organic buffer coating film 105 are deposited in this order over the dielectric film 103.
On the dielectric film 103, a testing-processing alignment mark 122 for use in alignment during, for example, a probe test, wire bonding or a process on the fuse wire and a stepper alignment mark 123 for use in alignment during formation of an opening in the inorganic passivation film 104 are provided. These alignment marks 122 and 123 and the external-component-connecting pad electrode 121 are formed out of an aluminum alloy film. The organic buffer coating film 105 has openings over the fuse wire 113, the testing-processing alignment mark 122, and the external-component-connecting pad electrode 121, respectively.
The stepper alignment mark 114 under the dielectric film 103 is formed, concurrently with the formation of the external-component-connecting wire 111, the ordinary wire 112 and the fuse wire 113, out of a copper film by a damascene process.
The testing-processing alignment mark 122 is generally formed in the vicinity of a corner of a chip. The passivation film 104 made of a silicon nitride film is not necessarily required so long as the reliability is ensured.
In the known semiconductor integrated circuit device, the testing-processing alignment mark 122 is an alignment mark for use in alignment during cutting or burning out of the fuse wire 113 with a laser, for use in alignment during a test performed by making the external-component-connecting pad electrode 121 in contact with a probe, for use in alignment during wire bonding, and also for use in alignment during dicing.
However, laser machining on the fuse wire of the circuit for redundancy replacement, for example, causes a problem of alignment errors leading to positional shift in, for example, the processed part. This is because the following reasons. The testing-processing alignment mark 122 is formed out of the aluminum alloy film constituting the external-component-connecting pad electrode 121, while the fuse wire 113 is formed out of the copper film constituting the external-component-connecting wire 111. Accordingly, all the errors in positioning the external-component-connecting pad electrode 121 relative to the external-component-connecting wire 111 are added to the alignment errors caused through the laser machining, and the errors are added to alignment errors caused by the laser trimmer.